During the fabrication of an array substrate, a planarized layer is normally formed before forming a pixel electrode, such that the step difference in the substrate is reduced, the pixel electrode can be formed more easily and the defect is reduced. Meanwhile, the planarized layer is generally formed as a relatively thick layer such that parasitic capacitance created between the pixel electrode and other conductive metal layers is reduced. However, the planarized layer has to be exposed when fabricating via holes in the planarized layer, such as the via hole connecting the pixel electrode and the TFT drain, or the via hole connecting the drive circuit and the gate line or the data line. As the planarized layer is relatively thick, a high exposure energy is required to obtain the desired via hole size, thereby reducing the exposing speed and decreasing the production efficiency.